CS Postdoc Profiles

Research Profile

To begin with, my main interests lie in the domain of computer architecture with sub domains: 3D integration and formal approach to chip design, cryptography, asynchronous methodology. Apart from that I became conversant in the art of design automation over the years, and participated in several TAPE-OUTs, a skill I don’t want to loose. That’s why I’m only interested in jobs that involves physical design of large scale systems.

I began my career as an electronics engineer in CDOT(Centre for Development of Telematics) which is the premier Telecom R&D lab in India. All the development work that I’ve done in CDOT both in hardware and low level software, and the hands on experiments with laboratory equipments have helped me immensely in my later jobs, in achieving my goals within time and efficiently.

Later I moved to France to pursue a PhD. program in ENST(Ecole Nationale Superieure des Telecommunications) Paris. In short the topic of the thesis is to find a suitable FPGA architecture for asynchronous circuits and implementing cryptographic IPs. I began with a theoretical study of interconnects and statistical representation of IPs(user netlists), then later proposed two different architectures which I pursued from start to end by fabricating experimental prototypes, development of CAD software and characterization. I was able to finish this amount of work with limited manpower in three years, thanks to the automation skills and acquaintance with Linux open source environment, and hands on experience inherited from my CDOT job. Details of these architectures and prototypes can be found in publications mentioned in the CV.

As a continuation of the theoretical work in the beginning, I was interested in alternative interconnect architectures. This drove me to publish a method of evaluation of diagonal interconnects based on statistical representation of IPs in FPGA 2009, a research effort much appreciated by my peers. For the same reason I became interested in 3D interconnect, and recently taped-out a prototype of 3D integration of MRAM with CMOS logic. This was part of my 9 months post doc experience at Institut d’Electronique Fondamentale(Univ. Paris Sud) in Paris which is a pioneer in MRAM research.

My CV

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: +33681507431

Categories Posted To:

Hardware / Architecture, Information Assurance / Security / Privacy / Cryptography