Over the last ten years, I’ve been living, studying and working in 3 different countries (Argentina, Spain and Norway), where I have had the opportunity to get to know and interact with people from contrasting cultures. Along that time, I have managed to keep an active social life while being among the top students, managing multiple projects without loosing attention to detail. I consider that many of the skills I’ve developed during this time are transferable and highly valuable in any dynamic work environment.

I’ve always been proactive, highly motivated, and eager to face challenges. From an early age, I have been self-taught. At just 14 years old, I designed a complete website about the solar system and space programs because there were no complete websites in Spanish at that time. It has always been one of my hobbies. Three years later, I decided to move to a different state (over 700 miles away from my home, family and friends) to study Computer Science Engineering. It wasn’t easy at all, but the combination of hard work, determination and sound organizational skills led me to complete my studies earlier than expected, as first graduate of the class. In early 2007, I moved to Barcelona, where in four years I finished two masters degrees and the PhD in High-Performance Computing with the European Doctorate Mention (obtained after a 3-months research stay at the Simula Research Laboratory, Norway).

I gained valuable experience in engineering working as intern at the Web Engineering team of my University in Argentina, where I developed skills on web-based systems and user interfaces. The commitment of my team was noticed and we were soon commissioned the development of the University’s Learning Objects Repository. Additionally, we were selected to represent the University in several programming contest, including the ACM International Collegiate Programming Contest. This experience developed my ability to take responsibilities and work under pressure.

Teamwork and projects were a constant part of my education, not only in Argentina but also in Spain, where I worked on a multidisciplinary and multicultural team at the Universitat Autonoma de Barcelona. Our research group had students and professors from different faculties and 14 differ- ent countries, such as Australia, Vietnam, India, Germany, Poland, Spain, Brazil and Argentina, among others. Learning to deal with this cultural and academical diversity was an enriching experience.

Best regards,
Gonzalo Zarza

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Phone: +34 608376797

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E-Mail: EMAIL OBFUSCATED

Phone: +81-90-9838-1039

I have applied runtime systems for optimizing and for dynamically detecting memory errors in programs. I also have experience in improving the performance and memory efficiency of runtime systems. I have worked on runtime profilers which are crucial to detecting opportunities in a program.

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• Visualization in the geosciences
• Uncertainty visualization
• HPC
• Simulation
• Perception based design
• 2D, 3D, and temporal visualization
• Virtual environments (CAVE-like environments, fishtank displays, display walls, 3D stereoscopic visualization)
• Bridging infovis and scivis

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E-Mail: EMAIL OBFUSCATED

Phone: 1-618-319-0828

Wireless Network-on-Chip can enable design of novel interconnection architectures that can achieve significantly better performance and dissipate orders of magnitude less power compared to the traditional wire based NoC. On-chip wireless links using millimeter-wave (mWNoC) metal antennas provide high bandwidth and low power communication channels over long distances. Hence they can be used to create short cuts between distant cores on the chip to provide fast and efficient traffic freeways. From standard network topologies used in traditional NoCs we move towards nature inspired ones like theSmall-World graph. Such topologies inherently have low average inter-core distances and scale very well with increase in size. I am working on the different methodologies for designing a mWNoC. My interest is also on related data communication protocols and component designs critical to make mWNoCs energy efficient and reliable. My future research goal is to establish a unified design methodology for nature-inspired massive multi-core chips utilizing various types of emerging interconnect technologies, like optical interconnects, on-chip transmission lines and wireless interconnects as long-range links.

For more information, please refer to my CV here.

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E-Mail: EMAIL OBFUSCATED

Phone: 509 339 7095

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E-Mail: EMAIL OBFUSCATED

Phone: 4166027066

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E-Mail: EMAIL OBFUSCATED

Phone: 949-838-4567

I began my career as an electronics engineer in CDOT(Centre for Development of Telematics) which is the premier Telecom R&D lab in India. All the development work that I’ve done in CDOT both in hardware and low level software, and the hands on experiments with laboratory equipments have helped me immensely in my later jobs, in achieving my goals within time and efficiently.

Later I moved to France to pursue a PhD. program in ENST(Ecole Nationale Superieure des Telecommunications) Paris. In short the topic of the thesis is to find a suitable FPGA architecture for asynchronous circuits and implementing cryptographic IPs. I began with a theoretical study of interconnects and statistical representation of IPs(user netlists), then later proposed two different architectures which I pursued from start to end by fabricating experimental prototypes, development of CAD software and characterization. I was able to finish this amount of work with limited manpower in three years, thanks to the automation skills and acquaintance with Linux open source environment, and hands on experience inherited from my CDOT job. Details of these architectures and prototypes can be found in publications mentioned in the CV.

As a continuation of the theoretical work in the beginning, I was interested in alternative interconnect architectures. This drove me to publish a method of evaluation of diagonal interconnects based on statistical representation of IPs in FPGA 2009, a research effort much appreciated by my peers. For the same reason I became interested in 3D interconnect, and recently taped-out a prototype of 3D integration of MRAM with CMOS logic. This was part of my 9 months post doc experience at Institut d’Electronique Fondamentale(Univ. Paris Sud) in Paris which is a pioneer in MRAM research.

My CV

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E-Mail: EMAIL OBFUSCATED

Phone: +33681507431