CS Postdoc Profiles » Hardware / Architecture

Haipeng Mi from University of Tokyo, Japan

tdomf_c5ea8 — Tue, 21 Jun 2011 14:13:00 +0000

solid background of electrical engineering and computer science.
capable for fast learning, self-motivated.

Contact Information

Phone: +81-90-9838-1039

apala guha from university of virginia

tdomf_c5ea8 — Tue, 17 May 2011 00:25:45 +0000

My research interests are in leveraging the special capabilities of runtime systems to improve the performance, power efficiency and security of applications. Runtime systems can trace the actual hot paths followed by programs through procedures, libraries etc. At the same time runtime systems can measure system events such as processor cycles elapsed and cache misses incurred. These two facts place runtime systems in a unique position to detect and exploit improvement opportunities. Therefore runtime systems can enhance the benefits offered by programming languages, compilers and architectures. I am also interested in using the opportunities detected by a runtime system to drive changes in architectures, compilers and programming languages.

I have applied runtime systems for optimizing and for dynamically detecting memory errors in programs. I also have experience in improving the performance and memory efficiency of runtime systems. I have worked on runtime profilers which are crucial to detecting opportunities in a program.

Contact Information

E-Mail: EMAIL OBFUSCATED

Jibonananda Sanyal from Mississippi State University

tdomf_c5ea8 — Mon, 16 May 2011 03:48:17 +0000

My research interests include:

Visualization in the geosciences
Uncertainty visualization
HPC
Simulation
Perception based design
2D, 3D, and temporal visualization
Virtual environments (CAVE-like environments, fishtank displays, display walls, 3D stereoscopic visualization)
Bridging infovis and scivis

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: 1-618-319-0828

Sujay Deb from Washington State University, Pullman, WA

tdomf_c5ea8 — Mon, 10 Jan 2011 00:42:23 +0000

Research Interest:
Modern multi-core chips are capable of integrating tens to hundreds of cores on a single die. They have become all-pervasive in several application areas involving intensive computations like weather forecasting, astronomical data analysis, bioinformatics and even consumer electronics. Network-on-Chip (NoC) was envisioned as a solution to the problem of such large scale integration by providing a plug-and-play communication backbone to enable easy scalability of the interconnect fabric. However, design of multi-core integrated systems beyond the current CMOS era will present unprecedented advantages as well as challenges, the former being related to very high device densities and the latter to soaring power dissipation issues. According to the International Technology Roadmap for Semiconductors (ITRS), the contribution of interconnects to chip power dissipation is expected to increase from 51% in the 0.13µm technology generation to up to 80% in the next five year period. This clearly indicates the challenges faced by the future chip designers associated with traditional scaling of conventional metal interconnects and material innovation. Even with architectural and design innovations interconnects still remain a critical bottleneck and hence the need to explore radical alternative technologies for sustainable improvements in power dissipation and performance on future generations of multi-core chips arises. One such radical technology is the on-chip wireless communication.

Wireless Network-on-Chip can enable design of novel interconnection architectures that can achieve significantly better performance and dissipate orders of magnitude less power compared to the traditional wire based NoC. On-chip wireless links using millimeter-wave (mWNoC) metal antennas provide high bandwidth and low power communication channels over long distances. Hence they can be used to create short cuts between distant cores on the chip to provide fast and efficient traffic freeways. From standard network topologies used in traditional NoCs we move towards nature inspired ones like theSmall-World graph. Such topologies inherently have low average inter-core distances and scale very well with increase in size. I am working on the different methodologies for designing a mWNoC. My interest is also on related data communication protocols and component designs critical to make mWNoCs energy efficient and reliable. My future research goal is to establish a unified design methodology for nature-inspired massive multi-core chips utilizing various types of emerging interconnect technologies, like optical interconnects, on-chip transmission lines and wireless interconnects as long-range links.

For more information, please refer to my CV here.

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: 509 339 7095

Chuck (Cheng Yan) Zhao from University of Toronto

tdomf_c5ea8 — Wed, 10 Nov 2010 23:32:33 +0000

? Optimizing and Paralleling Compiler
? Programming Language Design and Development Environment
? Dynamic Compilation, Binary Instrumentation, Translation and Optimization, Runtime Techniques
? High Performance and Distributed Computing (HPC)
? Computer Architecture and MultiCore Parallelism

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: 4166027066

Jungsook Yang from University of California, Irvine

tdomf_c5ea8 — Tue, 19 Oct 2010 21:17:26 +0000

http://multicoreresearch.com/about/

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: 949-838-4567

Sumanta Chaudhuri from Ecole Nationale Supérieure des Telecommunications (ENST), Paris

tdomf_c5ea8 — Wed, 18 Nov 2009 10:43:15 +0000

To begin with, my main interests lie in the domain of computer architecture with sub domains: 3D integration and formal approach to chip design, cryptography, asynchronous methodology. Apart from that I became conversant in the art of design automation over the years, and participated in several TAPE-OUTs, a skill I don’t want to loose. That’s why I’m only interested in jobs that involves physical design of large scale systems.

I began my career as an electronics engineer in CDOT(Centre for Development of Telematics) which is the premier Telecom R&D lab in India. All the development work that I’ve done in CDOT both in hardware and low level software, and the hands on experiments with laboratory equipments have helped me immensely in my later jobs, in achieving my goals within time and efficiently.

Later I moved to France to pursue a PhD. program in ENST(Ecole Nationale Superieure des Telecommunications) Paris. In short the topic of the thesis is to find a suitable FPGA architecture for asynchronous circuits and implementing cryptographic IPs. I began with a theoretical study of interconnects and statistical representation of IPs(user netlists), then later proposed two different architectures which I pursued from start to end by fabricating experimental prototypes, development of CAD software and characterization. I was able to finish this amount of work with limited manpower in three years, thanks to the automation skills and acquaintance with Linux open source environment, and hands on experience inherited from my CDOT job. Details of these architectures and prototypes can be found in publications mentioned in the CV.

As a continuation of the theoretical work in the beginning, I was interested in alternative interconnect architectures. This drove me to publish a method of evaluation of diagonal interconnects based on statistical representation of IPs in FPGA 2009, a research effort much appreciated by my peers. For the same reason I became interested in 3D interconnect, and recently taped-out a prototype of 3D integration of MRAM with CMOS logic. This was part of my 9 months post doc experience at Institut d’Electronique Fondamentale(Univ. Paris Sud) in Paris which is a pioneer in MRAM research.

My CV

Contact Information

E-Mail: EMAIL OBFUSCATED

Phone: +33681507431

Example Profile

cifell5 — Tue, 11 Aug 2009 18:14:16 +0000

My research Profile.