The Computing Innovation Fellows Project

Posted on: Thursday, May 20th, 2010
Broad Research Area: Hardware / Architecture, Mobile / Ubiquitous / Embedded Computing, Networks / Operating Systems, Numerical/Scientific Computing / HPC / Data-Intensive Scalable Computing, Programming Languages / Compilers

Research Interests:

In the past I have focused on high performance computers. I and my colleagues developed some of the first prototype computers that exceeded 200 MHz. However, in the past decade I have focussed on various aspects of low power computing. My research group developed the “Intelligent Energy Management” system used in many ARM cores. I was a co-inventor on the original razor patents, a circuit technology that is being deployed in many next generation low power cores to combat the growing effects of variation that occurs in smaller technology nodes. My research group has developed a series of ultra-low power signal processors targeted at mobile wireless baseband processing. They evolved into a commercial prototype developed by ARM, which led to a commercial spinoff, Cognovo. They will commercialize the processor and provide wireless software stack.
My group were among the first to propose replacing DRAM with non-volatile memory to reduce memory power, cost and footprint. His group has also been active in exploring new server architectures that combine “near threshold” technology and 3D chip stacking to drastically reduce system power consumption. They recently complete the tape-out of a 128-core multiprocessor that integrated the cores, caches and DRAM into a single 3D stack. The fabrication run was funded by a DARPA grant.
Finally, my group is exploring ways to build low power compact interconnect fabrics. We recently completed a compact 128 x 128 crossbar architecture that can sustain a bi-section bandwidth of about 1.3 terabits / second while consuming less than 130 mW.

Contact Information:

tnm@eecs.umich.edu +1 734 323 4613