Steven Nowick
Location: (New York, NY)
Personal Research Web Page: http://www.cs.columbia.edu/~nowick
Keywords: asynchronous and mixed-timing (i.e. mixed-clock, or synchronous/asynchronous) digital systems; high-performance and low-power systems; logic synthesis; computer-aided digital design; interconnect networks for parallel processors; GALS systems
Posted on: Thursday, June 4th, 2009
Broad Research Area: Hardware / Architecture
Research Interests:
My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels. As chips grow increasing larger and faster, power and design-time requirements become more aggressive, and timing variability becomes a critical factor, there are increasing challenges in assembling centrally-controlled synchronous systems. My goal is to make asynchronous digital design a viable option for designers.
Asynchronous design promises several key benefits: low power (where components are activated only when needed); high performance (some asynchronous systems can obtain average-case operating speeds, rather than be bound to worst-case); great robustness to timing variability and unpredictability; and modularity and composability.
There is a surge of interest in asynchronous design recently, for a variety of areas and challenges: (i) designing and integrating complex scalable digital systems and networks-on-chip (with multiple clock domains), which gracefully accommodate variability; (ii) ultra-low-energy and low-EMI applications (by dispensing with the global clock, and operating ‘on-demand’); (iii) embedded systems.
Recently, Philips has sold over 300 million asynchronous chips for moderate-performance
embedded systems: digital smartcards, passports, cell phones, pagers, and automotive. Through its incubated spinoff startup company, Handshake Solutions, an asynchronous ARM processor is offered through ARM Ltd. with 2.8x lower power than a comparable synchronous ARM (see http://www.handshakesolutions.com/products_services/ARM996HS/Index.html).
In my research group, there are currently six main project areas: (i) developing computer-aided design (CAD) tools and algorithms for the synthesis, optimization, analysis and verification of asynchronous designs, both for individual controllers and for entire systems; (ii) developing practical high-speed VLSl circuit structures, such as pipeline circuits; (iii) ultra-low-energy design (through computing-on-demand) of sensors and DSP’s; (iv) designing robust and flexible mixed-timing interface circuits, and asynchronous interconnect networks (NOCs), to accommodate mixed-clock and clocked/asynchronous timing domains, to enable the design of complex scalable multi-core systems with components operating at different clock rates; and (v) high-performance/low-energy arithmetic circuits; (vi) promoting technology transfer of my asynchronous CAD tools and circuit design styles to industry.
Recent successes from my group include:
- technology transfer to NASA Goddard Space Center:
Jointly designed experimental chip for laser space measurement, including use of our Minimalist CAD package (for controller design), exhibiting much lower area and power than comparable synchronous design
- technology transfer to IBM Yorktown:
Fabricated FIR filter chip (using async core with sync interfaces) exhibiting higher-throughput and lower-latency than the best comparable synchronous design from IBM
- tool development: CaSCADE package
CaSCADE is an asynchronous tool environment (jointly developed by Columbia/USC), with 3 Columbia tools, all downloadable with tutorials and user interfaces: (i) Minimalist (for asynchronous controllers); (ii) DES Analyzer (for performance analysis/timing verification of concurrent systems); and (iii) ATN-OPT (for robust asynchronous datapath design).
