Partha Pande
Location: (Pullman)
Personal Research Web Page: http://www.eecs.wsu.edu/~pande
Keywords: Multi-Core, Wireless Network on Chip, Hardware Accelerator for biocomputing
Posted on: Wednesday, April 28th, 2010
Broad Research Area: Hardware / Architecture, Numerical/Scientific Computing / HPC / Data-Intensive Scalable Computing
Research Interests:
Current Research Interests: My current research principally revolves around the broad topic Network on Chip (NoC), which has emerged as the communication backbone for multi-core chips. With my graduate students and collaborators I am working on the following projects.
•On-chip wireless communication network: Recent research has established characteristics of silicon integrated antennas for intra- and inter-chip communication. Moreover excellent emission and absorption characteristics leading to antenna like behavior in carbon nanotubes (CNTs) are observed recently. In this project we are working on the design methods for wireless NoCs with different types of on-chip antennas.
•Reliable and Low Power NoC: We have designed a family of joint crosstalk avoidance and multiple error correction codes (CAC/MEC) and demonstrated how a low power and reliable NoC can be designed by incorporating these CAC/MEC codes.
•Three dimensional (3D) NoC: NoC has emerged as the communication backbone for the multi-core chips. The performance improvement arising from the architectural advantages of NoCs will be significantly enhanced if 3D ICs are adopted as the basic fabrication methodology. The amalgamation of two emerging paradigms, NoC and 3D IC, allows for the creation of new structures that enable significant performance enhancements over more traditional solutions. In this project we are investigating characteristics of 3D NoCs.
•Network-on-chip based hardware accelerators for Biocomputing: The gap between data generation and data processing is rapidly widening in biocomputing applications, and to close this gap it is imperative to assimilate the latest of breakthroughs in the Integrated Circuit (IC) design community into mainstream biocomputing research. Integrating huge number of processing cores on a single chip can help realize orders of magnitude improvement in performance and eventually will bridge the gap between data generation and data processing. In this project our aim is to design NoC-based hardware accelerators for different biocomputing applications, like sequence alignment and phylogenetic tree construction
Contact Information:
pande@eecs.wsu.edu
