John Darringer
Location: (Yorkstown Heights, NY )
Personal Research Web Page: http://domino.research.ibm.com/comm/research.nsf/pages/r.da.html
Keywords: Performance, power modeling, thermal analysis, floorplanning, integrated system, architectural trade-off, 3D, chip integration, physical design.
Posted on: Wednesday, April 28th, 2010
Broad Research Area: Hardware / Architecture
Research Interests:
Early 3D Chip Planning
Realizing the potential that 3D VLSI offers, requires system and chip architects to consider a broader range of options than the may have thought about in the past. For example, the placement of functions on the different strata of a 3D VLSI chip impacts a variety of features and attributes whose implications are not fully known: latencies that affect performance; power density that affects temperatures, power distribution demand and reliability; number and location of TSVs (thru-silicon vias) that affect wiring congestion and logic layout; proximity of macros that affects noise coupling among layers, etc.
To improve the linkage between the performance modeling environment and the physical planning environment for 3D VLSI chip design, we are integrating diverse forms of analysis to enable early and accurate identification of performance, power density, thermal, C4 and TSV current, IR drop and other physical issues. The goal is to help system architects to rapidly make trade-off decisions. In addition, we are developing a linkage from the early abstract design to an initial “detailed” layout that captures the design decisions and enable detailed chip integration. Such an integrated 3D planning environment provides an environment for new optimization tools to further assist system architectsarlky arl
