Chung-Kuan Cheng
Location: (San Diego, CA)
Personal Research Web Page: http://www.cse.ucsd.edu/users/kuan/
Keywords: circuit simulation, physical layout, high performance low power interconnect, power ground network and clock analysis and designs.
Posted on: Thursday, June 4th, 2009
Broad Research Area: Hardware / Architecture, Numerical/Scientific Computing / HPC / Data-Intensive Scalable Computing, Theory / Algorithms
Research Interests:
High Performance Low Power Interconnect
Analysis, Design, and Optimization
We plan to continue, and further extend our work on interconnect
analysis, design, and optimization with an emphasis on high speed
and low power under parameter variations.
Our research tackles the challenges of the power ground distributions,
clock networks, and signal buses as the technology scales.
(1) power ground distribution: As the VLSI technologies scale,
the power noises integrity have created serious signal integrity
problems. The conventional methodology of bounding the target impedance
has become very expensive. Our goal is to suppress the peak voltage
noises instead of the peak impedance. We will identify the worst
stimulus of the system, devise robust controls of the system
activities, adjust the equivalent series resistance of the
decoupling capacitors to restraint the antiresonance, and
allocate the power pins of chip carriers and PC boards for
global optimization.
(2) clock distribution: The analysis of the clock timing has
become one bottleneck of the design process in terms of CPU
time and memory storage. Recently released location-based
on-chip variations (LOCV) standard was proposed to tackle the
statistical parameter variations. However, the LOCV standard
aggravates the demand of computation power and memory capacity.
We will study new algorithms to speed up the LOCV analysis of
common segments of clock paths and reduce the memory requirement.
(3) on-chip shared bus logic and topology:
For on-chip buses, the signal delay and power consumption
are becoming more significant as the technology scales.
We have invented a graph topology with gated logic to improve
the system performance. We will continue to study the design
algorithms and circuit architectures for the best performance
of the buses.
Contact Information:
email obfuscated - click to reveal, 858 534-6184
