My Carbon group within CSAIL MIT is working on a new operating system for massive multicores and cloud computing called Factored Operating System (FOS). We are also working on multicore architectures for 1K cores. Postdoc positions are available in both these areas.

Research in high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, nanoelectronics, spintronics, printable electronics, SOC design, subVolt switch design, aging and wearout.

Intra-die process variations in nm technology nodes pose significant challenges to robust design practices. Geometric variations along with random dopant fluctuation effects have had significant impact on Logic/Memory functionality/yield. The inaccuracies in the models and variabilities in the process are more pronounced and key is to understand the variability effects. Innovative analysis techniques as well as methodologies are needed to counteract the variability issues. Our team is heavily engaged in this activity.

Smart statistical and numerical techniques are key for understanding the variability in VLSI circuits. These techniques need to be highly efficient to be used by designers. New algorithms to achieve speed-up in these techniques are essential. Extension of these smart algorithms beyond the VLSI domain would be critical to achieve accurate and computationally practical would benefit such fields (e.g application to medical field). We are exploring new algorithms and their applications to fields other than VLSI.

As the VLSI circuits scale power and performance remain the top issues. Developing efficient circuit techniques based on emerging devices (FinFet derived, nano-devices) needs extra attention.
We are involved in fabrication of such circuits. Also we are engaged in modeling of 3-D structures and the thermal management of multilevel domain.

Scaling and manufacturing of alternate memories such as MRAM and PCM would help to replace DRAM. Variety of activities from modeling to fabrication are explored in our team

I am broadly interested in topics around cloud computing, including software for datacenter management, cluster file systems, techniques for managing data center power, hybrid cloud technologies, programming frameworks, operating systems, and cloud applications. As part of my research, I manage a 200-server cluster designed to enable experimentation with prototype system software, so our research facility provides ample opportunity for empirical evaluation.

The main focus of my work is on energy efficient computing. Energy consumption has already become one of the most important design parameters in electronic systems. In large scale data centers it is because of the high cost of powering and cooling the equipment. We are currently working on design of VM level energy management strategies that integrate measurement of power, temperatures and workload characteristics, while monitoring QoS of applications running within VMs. In addition, we are evaluating how to integrate SmartGrid information with VM level energy management strategies and how to leverage accurate predictors of the availability of renewable resources that we developed. This work is funded by a large center on Multiscale Systems (www.musyc.org).

We recently also won an NSF Expedition on variability. The work here focuses on how to address variability issues in general purpose systems due to environmental, manufacturing and vendor differences. The current focus is on cooling and thermally aware scheduling techniques for 2 and 3D integrated server and mobile systems.

Limited bandwidth, increase in power dissipation at longer communication distances create a major communication bottleneck in high-performance computing (HPC) systems, affecting not only their performance, but also their scalability. My research interests include designing interconnects for high performance computing systems at all levels: on-chip, chip-to-chip and rack-to-rack.

Come join a large well-funded research effort in cloud computing! Over 10 Carnegie Mellon University professors and 4 Intel Labs researchers are teaming up to drive a common research agenda in cloud computing. Contrary to the common practice of striving for homogeneous cloud deployments, we are exploring the use of specialization as a primary means for order of magnitude improvements in efficiency (e.g., energy), including the design of new platform configurations based on emerging technologies like non-volatile memory. Other research themes include automation at cloud scale (e.g., resource allocation/scheduling, problem diagnosis), big data analytics beyond search (including over live data feeds), and new paradigms for meshing client devices and cloud. Our research lab is a great place to do research. It combines the resources of a well-funded industrial research lab (e.g., our lab’s cluster has 1500+ cores and 600+ terabytes of storage) with the academic freedom of a university. As for me, I am the Intel PI for the cloud computing efforts. I have over 120 publications (cited 10,000+ times), including co-authoring award-winning papers at ICDE, ISCA(2), NSDI, PLDI, and SIGMOD, as well as 13 other papers that were selected for “best papers” journal issues for their respective conferences (including ICFP, PODC, PODS, SIGCOMM, SPAA, and VLDB). I have served on 50 program committees for international conferences (including program chair, vice-chair, etc), and have helped place junior collaborators on a number of top committees. I am on the editorial board of the Journal of the ACM, and an ACM Fellow.

In response to the increasing challenges in maintaining technology advancements through traditional scaling at a pace consistent with Moore’s law, alternative methods to achieve enhanced system level performance are becoming increasingly important. 3D Technology has the potential to provide significant performance enhancements for several generations. Realization of this technology will require collaborative research and development across system architecture, design, and technology. Significant changes to the basic circuit design, layout procedures and tools flow, as well as the routing of global signals and supplies (power/ground distribution, clock distribution, and I/O), will be required to accommodate the 3D technology features in stacked active chip designs. These changes can only be understood through a detailed evaluation of the impact of each of the unique 3D technology elements on the design. The Research Division is involved in leading the exploration of these new aspects of 3D VLSI chip design for future systems.

I have broad interests in systems spanning applications, system software, networking, and architecture. Current interests include: 1) Cloud/Grid applications, system software, and architecture; 2) Computer Architecture for Exascale computers; and 3) Programming models and tools for post-Moore’s Law computing substrates.

HP Labs Immersive 3D

HP Labs is conducting research using large display walls, 2D and 3D. HP has multiple product and services offerings in the so-called “Big Walls” area ranging from digital signage to large telepresence facilities (such as HP’s Halo). Our research extends this by following two main, intertwined branches. The first examines a new style of 3D entertainment, and the other targets commercial and industrial uses for 3D enabled operations centers, brainstorm or war rooms, and control centers. We are conducting research in:
• Computer vision, image processing, and recognition,
• Robust multi-imager and multi-camera modeling and calibration,
• 3D data visualization,
• High performance computation, transport, and imaging on hardware accelerated platforms (CPUs and/or GPUs),
• Novel human-big wall interaction modalities across heterogenous systems, and
• Local and remote collaboration technologies.

We have publicly shown our Immersive 3D Entertainment efforts with events at the 2010 Sundance Film Festival and the Earth Wind and Fire Concert at 2011 CES in Las Vegas (links listed below). HP’s goal is to experiment with non-standard aspect ratios (e.g. 3:1 for concert stage, 5.5:1 for basketball court) to allow the audience to experience the event as though you are seated at the best seat in the house. This is a break from the traditional movie view from the director’s eyes and allows the audience to “look around” and soak up the scene which works so well in 3D. To do this, we are experimenting with large multi-projector 3D displays (Pluribus), multi-imager camera capture (Herodion), and advanced digital image pipelines (Pericles). We conduct in-situ laboratory studies at entertainment events such as concerts, sports events, fashion shows, and other gaming.

We have built an experimental operations center with multiple 2D and 3D walls and other services. Together with many HP customers, we are exploring novel ways to use Big Walls to address issues in areas such as disaster recovery, emergency response, hospital wards, city monitoring and management, mergers and acquisition planning, product planning, and supply chain management. We are creating a next generation capability by using Big Walls together with mobile devices, touch surfaces, 3D data visualization techniques, and techniques for displaying, manipulating and visualizing large amounts of unstructured data. In addition to our research, we participate in the real world by providing support for HP’s worldwide operations centers and the HP supported gallery at the Newseum due to open in 2012.

Links to entertainment reviews
HP 3D Live: CES Earth Wind and Fire concert

http://blogs.forbes.com/oliverchiang/2011/01/08/ces-hp-believes-in-3-d-too-but-on-a-larger-scale-much-larger/

http://www.monstercable.com/events/ces2011/3dexperience.asp

http://h20435.www2.hp.com/t5/The-Next-Bench-Blog/Earth-Wind-and-Fire-Going-Large-Live-and-in-3D-at-CES/ba-p/60745

http://www.hardwaregeeks.com/index.php/site/comments/hp_streams_concert_live_in_3d/

http://venturebeat.com/2011/01/14/hp-streams-earth-wind-fire-in-live-3d-on-a-huge-screen/

2010 Sundance Film Festival

http://philmckinney.com/archives/2010/01/sundance-and-3d.html

http://h20435.www2.hp.com/t5/The-Next-Bench-Blog/Stories-in-3D/ba-p/52743

HP Newseum announcements

http://www.hp.com/hpinfo/newsroom/press/2010/100930a.html

http://www.newseum.org/news/2010/09/hp-announcement.html

Ginkgo BioWorks is a young company out of MIT with the mission of making biology easier to engineer. We engineer organisms to solve challenges across a range of industries from fuels to pharmaceutical production. We aren’t trying to study biology, we are trying to build it – constructing, editing, and redesigning the living world. Our bioengineers make use of an in-house pipeline of synthetic biology technologies to design and build new organisms.

We are looking for a computing postdoc who is passionate about developing CAD tools for the engineering of organisms. You probably have a background in comparative genomics, computational biology, metagenomics, or other similar areas. You have likely been building computational tools to study natural biology — but at Ginkgo you would have the opportunity to apply your skills and tools to the challenge of engineering new organisms.

At Ginkgo, our organism engineers have immediate demands for expanded tools to support organism design. We believe that we provide a unique environment for someone to cut their teeth on real CAD problems in biological engineering. Lastly, we’d be happy to serve as mentors for CIFellows if you are pursuing that fellowship.

My research focuses on two main topics and their interdependence: the role of physical constraints in processor design, and the architecture of future multi/manycore platforms.

Despite continuing availability of plentiful transistors thanks to Moore’s Law, physical constraints—chiefly temperature, power delivery, energy efficiency, and reliability—now prevent straightforward scaling of processor performance. New design-time and run-time techniques are needed to address these limitations, as well as improved modeling and capabilities. Our group at UVA has a long track record of high impact work in these areas.

These physical constraints, combined with the memory wall, will constrain the types of designs that are possible, requiring both novel combinations of cores and novel memory hierarchies. Our group is exploring these issues, especially focusing on the memory hierarchy, how to organize cores around bandwidth limitations, requisite programming support, and how to incorporate these techniques within power, thermal, and reliability constraints.

Design, modeling, measurement, and analysis of conventional and biologically-inspired high-performance computer architectures and their interaction with state-of-the-art optimizing compilation systems, modern operating systems, and scientific, commercial, and intelligent applications.

The Interface Ecology Lab imagines and develops integral and sensitive human-centered computing to support nuanced and exciting aspects of life, including how we form and express ideas and intentions, how we learn and innovate, how we gesture and communicate, how we coordinate and cooperate, how we participate and share, how we function under stress, and how we respond to crises. We connect diverse methodologies, engaging an interface ecosystems approach to engage computing in holistic avenues of human experience.

We have just developed an innovative multi-finger sensor, ZeroTouch. We are now poised to integrate ZeroTouch into interactive environments, developing new embodied bi-manual and free air interaction techniques and experiences.

We have released the open source meta-metadata language and architecture, for authoring platform-independent wrappers for heterogeneous information sources. Meta-metadata supports information extraction and knowledge integration. It facilitates writing programs that enable new human experiences of information visualization, physically-based modeling, and embodied interaction. Research here involves new knowledge semantics and modeling, on the one hand, and new interactive visual applications, on the other. Social media and digital libraries are connected.

We are developing special relationships with disaster response organizations. Texas Task Force 1 engages in major disasters, such as 9/11, and hurricanes Katrina, Rita, and Ike. TEEX Disaster Preparedness and Response runs an internationally-renowned academy for first responders. We are engaged both in developing zero fidelity simulation games for education, and in creating innovative multi-surface information systems for crisis response.

The typical search interface is great for finding a single element of information, but weak for information-based ideation tasks, in which the human goal is to to develop ideas with support and stimulus from information. The combinFormation platform reconceptualizes information-based ideation support as mixed-initiative information composition, integrating browse-search-collect-visualize-and-organize, while representing each collection as a connected whole. To validate composition, information-based ideation metrics and grounded theory are extended and synthesized, developing formative and summative evaluation methodologies. Application contexts include thesis writing in computer science, and design in architecture and mechanical engineering.

Digital integrated circuits, computer arithmetic, cryptography accelerators, computer architecture.

Harvey Mudd College is a top-rated undergraduate teaching college. Our focus is on excellence in undergraduate teaching. Research largely complements this focus by providing undergraduates a chance to work on important unsolved problems. A CI Fellow at HMC would be heavily involved in undergraduate education in areas such as digital design and computer architecture, VLSI, microprocessor-based systems, and senior Clinic projects. An opportunity exists for a 2-year visiting position from 2011-2013.

My group works on low-level systems, mostly recently on securing systems using virtual machines, trusted platform module (TPM) hardware, and mandatory access control operating systems.

We also have an ongoing interest in GPU computing, specifically in integrating the GPU into system-intensive tasks, like the file system. We build and evaluate large systems.

With each new generation of bulk complementary metal-oxide semiconductor (CMOS) technology, steady miniaturization of transistors has yielded continual improvement in the performance of digital circuits. The scaling of bulk CMOS, however, faces significant challenges in the future due to fundamental material and process technology limits. The primary obstacles to the scaling of bulk CMOS to the 22nm technology node include short-channel effects, sub-threshold leakage, and device-to-device variations. It is expected that the use of double-gate field-effect transistors (DG-FETs), the most popular of which are FinFETs, will be necessary to overcome these obstacles to scaling. My group is actively investigating novel FinFET-based circuits, memories, and computer architectures.

3D ICs are emerging as solutions to the problems of long interconnect and memory bandwidth. In addition, such ICs enable “More than Moore’s Law” applications that allow heterogeneous integration across their multiple layers, opening up exciting possibilities for innovative SoC design. We are investigating various 3D ICs that employ novel system designs comprising embedded processors, RF circuitry, FPGAs, and memories.

Power consumption has become one of the most important metrics in evaluating a circuit today. This is due both to environmental considerations and to a variety of technical requirements such as prolonging battery life in portable devices, reducing chip packaging and cooling costs, and increasing reliability. To that end, my group has been researching low-power FPGAs, interconnection networks, and CMPs. We are also interested in the related important problem of dynamic thermal management.

Security is emerging as an important concern in the embedded system area. Security of embedded systems is often compromised due to vulnerabilities in the “trusted” software they execute. Security attacks exploit these vulnerabilities. My group has been working on a hardware-assisted paradigm as well as virtualization to enhance embedded system security by detecting and preventing the execution of malware. We are also actively investigating how to make biomedical devices secure from new attack mechanisms that have been recently developed.

If not enough care is taken when testing an IC, even a good die may be inadvertently damaged by the high temperatures caused by test application. Although low-power test has a rich history, temperature-aware test is a new field. We are currently developing various temperature-aware test methodologies.

The quest for quantum computers is gathering steam. Various quantum algorithms have been developed that show speeds orders of magnitude above those of classical computing. My group is interested in automatically obtaining optimized quantum logic circuits from these quantum algorithms.

Energy consumption has also become an important issue, especially from the point of view of carbon dioxide emissions. In the U.S., buildings consume 40% of the total energy. Thus, reducing the energy consumed in buildings can have a substantial national impact. My group is developing various types of sensors to reduce the electricity/heating costs in buildings.

Bio and Prior Work: Martonosi’s research interests are in computer architecture and mobile computing, with an emphasis on energy-efficient systems. In the field of processor architecture, she has done extensive work on power modeling and management and on memory hierarchy performance and energy. This has included the development of the Wattch power modeling tool, the first architecture level power modeling infrastructure for superscalar processors. In the field of mobile computing and sensor networks, Martonosi led the Princeton ZebraNet project, which included two real-world deployments of tracking collars on Zebras in Central Kenya.

Current and Future Projects:

1) In the processor architecture area, Martonosi’s group is currently exploring system-level interfaces to allow nimble management of power, performance, and parallelism tradeoffs in chip multiprocessors and MPSoCs.

2) She is also researching power-performance control problems in large-scale data centers. Her students are studying a range of optimizations that are either localized within single data centers or spread across regionally-distributed data centers. Together, these techniques are aimed at reducing data center energy usage, better managing workload and power spikes, and better optimizing the use of electricity acquired from green sources.

3) Martonosi’s work in mobile computing includes projects improve the location-awareness of mobile cellphone apps, while also abiding by privacy and security expectations. This includes a mix of cross-phone collaboration, location modeling/estimation, and other techniques. Her group is also leading the C-LINK effort which uses mobile computing techniques to bring cost-efficient, low-latency internet access to developing regions.

My main research interests are in the areas of
- High-performance processors
- Memory hierarchy, prefetching, cache coherence
- Multi-cores and multiprocessors
- Power and temperature management
- Compiler and architecture co-design

information integration, query-evaluation algorithms, temporal reasoning,
automata-theoretic algorithms, firmware validation, protocol synthesis, constraint satisfaction, discrete techniques in robotic motion planning

My research focuses on the interaction between the architecture and software of computer systems and underlying hardware implementation challenges. These challenges include power, reliability, and variability issues across embedded and high-performance computing systems. A basic tenet of my research is that architecture design must be cognizant of these implementation issues, and that multi-layer solutions spanning circuits, architecture, and software can provide significant advantages.

It is now widely recognized that current commercial many-core systems are simply not good enough: most programmers can’t handle them. Therefore, alternatives must be developed. Anticipating this problem over a decade ago, the Explicit Multi-Threading (XMT) framework has been under development at the University of Maryland. XMT is a general-purpose many-core computing platform with the vision of a 1000-core chip that is easy to program but does not compromise on performance.

XMT is built to support the PRAM theory of parallel algorithm, which is second in its wealth only to the serial algorithms. Since four decades of parallel computing research provided no real alternative to the PRAM, the XMT project sought to draft specifications for the general-purpose many-core desktop of the future, by first inventing hardware and software support for the abstractions developed by PRAM algorithmics — a task deemed impossible by architecture researchers prior to the accomplishments of the XMT project.

A 2010 status report of XMT appears in U. Vishkin, Using simple abstraction for reinventing computing for parallelism, CACM, January 2011. Order of magnitude speedups, dramatic advantages on teachability from middle school to graduate courses have been demonstrated. And favorable student ranking for achieving speedups relative to standard platforms have been demonstrated.

So far, XMT has spanned applications, parallel algorithms, compilers, HW/SW and education of parallelism. Research opportunities building on this promising foundation include now also CS education, bioinformatics, machine learning and other applications, security, OS, and SW architectures.

There is so much more to the potential of many-core parallel computing than the horizons of commercial hardware offer!

I direct the UCSD Center for Dark Silicon, which is dedicated to maximizing the amount of computation we can get out of a single square centimeter of silicon. Dark Silicon refers to factors that prevent us from using this resource at its full potential. There are three causes to dark silicon: a) power limitations because of poor CMOS scaling, b) overly large software engineering costs for parallelizing programs for multicore chips, and c) lack of parallel application domains.

My research attacks each of these problems by 1) reinventing processor design to make use of dark silicon, 2) utilizing existing cores better through better parallel software engineering tools and 3) finding new parallel application classes to put cores to work.

I co-direct the GreenDroid Mobile Applications Processor pojects, which employs Conservation Cores, automatically-generated energy saving coprocessors to fight dark silicon and is part of the Arsenal Project. It has been featured in MIT Technology Review, EE Times, and slashdot.org.

I direct the Kremlin project, which has developed a tool that, given a serial program, tells you which regions to parallelize. It’s like gprof, but for parallelization. It uses a novel dynamic analysis called hierarchical critical path analysis. It’s appeared in PLDI, PPoPP and HOTPAR. We have some more novel extensions for GPUs that we are working on.

I also direct the effort that developed the San Diego Vision Benchmark suite, and an effort to adapt manycore processors for Cloud computing.

Post-doc positions are available in the context of the following broad projects:

1) the development of methodologies and tools for the design and programming of heterogeneous multi-core system-on-chip;

2) the design of energy-efficient high-performance networks-on-chip including also networks that leverage emerging silicon-photonics technologies;

3) the design of cyber-physical systems and distributed embedded systems, including systems based on wireless sensor network (WSN) technologies.

Strong industrial collaborations with leading information technologies and engineering companies are maintained for each of these projects.

Luca Carloni is an associate professor of Computer Science at Columbia University where he leads a research program in the areas of design technologies, computer-aided design, embedded systems, and high-performance computer systems.

Prof. Carloni received the Faculty Early Career Development (CAREER) Award from the National Science Foundation in 2006, was selected as an Alfred P. Sloan Research Fellow in 2008, and received the ONR Young Investigator Award in 2010.

While a PhD student at UC Berkeley he received the Demetri Angelakos Memorial Achievement Award in recognition of altruistic attitude towards fellow graduate students. He is an associate editor of the ACM Transactions in Embedded Computing Systems and the IEEE Transactions on Industrial Informatics and has served in the technical program committee of several conferences. He served as the technical program co-chair of NOCS’10, EMSOFT’10 and MEMOCODE’10.

For a complete list of publications please see http://www.cs.columbia.edu/~luca

My research is in power efficient computing. Power efficiency can be achieved on various level from algorithm, architecutre, microarchitecture and circuits. I enjoy learning new things and would not mind working with researchers from different backgrounds.

My research focuses on computer architecture, including (but not limited to):

- Processor Microarchitecture
- Power-efficient or resilient microarchitectures
- Multiprocessor and chip multiprocessor systems design
- Memory systems design
- Cache compression
- Performance evaluation of multi-threaded commercial workloads

VLSI CAD for More Moore (nanolithography beyond 22nm) and More-than-Moore (3D-IC, nanophotonics, etc.);
Physical design and technology co-optimization;
Computational lithography;
Vertical integration of architecture/CAD/circuit/technology;
Design/automation of emerging technologies

Design, EDA, and architectures for 3D ICs;
Emerging memory technologies;
Variation-aware design methodologies and architecture;
multi-core/many-core architecture;

design, implementation, and evaluation of advanced transactional programming features from hardware through language and benchmarks; automatic generation of compiler back-ends from machine and IR descriptions; automatic generation of corresponding efficient cycle-accurate simulators; proving properties of data abstractions as related to transactional programming; the chaotic nature of computer systems performance and application of chaos theory; machine learning in systems problems, particularly in compilers and virtual machines; virtual machines / managed run-time systems for parallel languages on many-core platforms

We are pursuing exciting systems architecture projects that crosscut: multicore processor architecture, heterogeneous computing, intelligent storage device architecture, OS design, and memory hierarchy design. Further, we look at various issues w.r.t. solid-state storage class components at different system levels. We have access to industry-strength SSD boards and build experimental systems using simulation and emulation techniques.

My research interests lie in two primary areas: design of high performance, but energy efficient computer systems and compilation for heterogeneous multicore systems. Traditionally, high performance and energy efficiency have been competing goals and designers have to select one of these objectives. The CCCP group focuses on achieving both by improving the fundamental efficiency of computation through customization of hardware to the target application domain and the use of flexible accelerators to accelerate small portions of accelerators. Under investigation are low-power graphics processing units, flexible single instruction multiple data accelerators, and compute engines for control-intensive code.

The second area of focus is compilers for heterogeneous multicore systems. We are currently focusing on the streaming model and an implicitly streaming model that extracts stream program behavior from C/C++ code. The compiler automatically customizes the streaming computation for graphics processing units, SIMD accelerators, and multicore systems. Compiler-generated CUDA from a streaming specification is machine independent and can outperform hand optimized CUDA on many applications.

Our goal is to understand how currently-available and emerging non-volatile memories can enable new applications, improve performance, and increase efficiency. To understand the impact of these technologies, we construct prototype hardware and software systems, including one of the world’s first phase-change memory storage arrays.

We are particularly interested in the interaction between storage system hardware and software, and we have shown careful engineering in both areas is essential to fully utilize the raw performance that these technologies can provide. For instance, we have shown that implementing some components of the file system in hardware can dramatically increase throughput, reduce latency, and save power.

We take an interdisciplinary approach to improving application level performance. For instance, upcoming projects include implementing specialized file system, database, and application components to fully exploit the performance that our prototype systems can deliver and to understand how these software systems must change in light of fast non-volatile memories. We are working closely with experts in each of these fields at UCSD and at other universities.

My research falls inside the fields of power-aware computer architecture, power-agile computing/OS and low-power VLSI design.

I have three main projects that a potential postdoc fellow could develop drive and mentor the PhD students on the project:

• AfterBurner: Efficient Performance Scaling via Post-Retirement Processing. NSF funded project with Amir Roth, UPenn that targets region of low ILP in modern out-of-order microprocessors. We need a fellow with a strong microarchitecture background to drive the simulator development of this project.
• Accelerator-based computing. As the industry moves to SoC based systems in the mobile and server space future systems are going to be composed of heterogeneous accelerators and cores. We need someone with strong application profiling skills (or binary instrumentation skills) to help profile the accelerators that my VLSI students are trying to build.
• Power-agile computing. See the HotOS 2011 paper. We are trying to model future heterogeneous systems composed of difference types of cores, memory, and storage. Potential fellows should have experience with architecture simulators and operating systems.

My primary interest is in programmable graphics hardware and the things you can do with it. Much of my recent work is at the intersection between rasterization and ray tracing or volumetric effects, including monte-carlo tracing for soft shadows, multiple refractions, translucent objects, and higher-order GPU traced primitives for isosurface rendering.

Meanwhile, I also maintain interests in GPU programming for non-rendering purposes. Recent works in that vein include image segmentation, longest common subsequence, and multilevel multidimensional scaling.

My key research interests are: making it simpler to write, debug and deploy parallel programs to address the concurrency challenge; develop energy-aware programming models; exploring systems software for non-volatile main memory. Sample research projects include making multiprocessor systems deterministic, dynamic concurrency bug avoidance, debugging, concurrency exceptions for failstop behavior of race condition, energy-aware programming models, etc.

My most recent work has focused on cache and memory hierarchy design. We are currently exploring if memory chips can be augmented to improve their energy, latency, and reliability characteristics. In addition, we are considering improvements to the memory channel (both electrical and photonic) and the memory controller. We are also interested in improving hit rates and data proximity in last-level caches.

1. Usability and information visualization applied to biomedical informatics, including bioinformatics and clinical informatics
2. Collaborative data portals in support of bioinformatics, including semantic applications.
3. Translational research tools, including social networking & collaboration finding, coordination tools and resource ontology systems.

We study the design and fabrication of nanostructures as applied specifically to the fabrication of future computing and sensor systems: devices-to-computer architecture. The terms ‘nanocomputing’ or ‘molecular computing’ refer to the fabrication techniques (e.g., self-assembly) that have the potential to create devices with critical dimensions near the molecular scale (i.e., < 10nm). However, defects introduced during self-assembly require a change in the way we design and build these systems.

Self-assembly is a bottom-up fabrication technique that can be used to achieve molecular scale resolution. The goal is to use these structures to integrate active nanoelectronic devices into a fully self-assembled circuit technology – and to study the new forms of computer architecture that the technology enables. To do this we have adopted a broad and vertical research approach to cover topics in the synthesis and design of DNA nanostructures, nanoscale device and circuit modeling, and studies of emerging computer architectures.

Work in this area requires a deep interest in pushing the frontiers of computing and a traditional background in hardware/software design, computer architecture, or systems. Techniques specific to DNA nanotechnology and the "device side" are acquired here through hands-on laboratory work and analysis.

I am interested in all aspects of multicore processor architectures; current and future focus is on the memory hierarchy design and the interaction between computer architecture and the operating system. We have also worked on efficient simulation techniques to evaluate multicore systems with hundreds of cores.

I am also interested in applying new memory technologies, such as phase change memory, to small- and large-scale systems. Focus is on developing new low-energy main memory architectures for data centers and researching new hybrid-technology storage systems.

Design, modeling, measurement, and analysis of conventional and biologically-inspired high-performance computer architectures and their interaction with state-of-the-art optimizing compilation systems, modern operating systems, and scientific, commercial, and intelligent applications.

My primary research interests are in
data mining/machine learning, high performance computing and database systems.
In our lab we seek to develop efficient and novel
algorithms for managing and analyzing complex data. Our recent research
is particularly motivated by
applications that arise in the area of
network science (specifically biological networks and social networks).
Below we briefly describe two projects in these areas, for others
please refer to the personal and laboratory web pages listed.

1. Architecture Conscious Algorithms and Systems:
Here we have been looking at ways
in which various algorithms (XML indexing, Network motif mining, Frequent
pattern mining) can be re-designed to fully exploit the capabilities
of current day architectures ranging from GPUs to
multicores to supercomputing systems. Of particular interest
is the development of an effective infrastructure enabling such algorithms to
scale to very large data stores .

2. Algorithms and Systems for Network Science:
Here we seek to unravel common principles, events, algorithms and tools that
govern network behavior across different domains ranging from social
networks to biological networks. Of particular interest here are not just
algorithms for module discovery, link discovery,
anomaly detection and event detection
but also usable systems infrastructure that can enable
researchers to effectively
query, visualize,
and analyze such networks under various trust, probabilistic and
provenance models.

If you are interested to learn more about our activities in these areas please feel free to contact me as noted herein.

In the past I have focused on high performance computers. I and my colleagues developed some of the first prototype computers that exceeded 200 MHz. However, in the past decade I have focussed on various aspects of low power computing. My research group developed the “Intelligent Energy Management” system used in many ARM cores. I was a co-inventor on the original razor patents, a circuit technology that is being deployed in many next generation low power cores to combat the growing effects of variation that occurs in smaller technology nodes. My research group has developed a series of ultra-low power signal processors targeted at mobile wireless baseband processing. They evolved into a commercial prototype developed by ARM, which led to a commercial spinoff, Cognovo. They will commercialize the processor and provide wireless software stack.
My group were among the first to propose replacing DRAM with non-volatile memory to reduce memory power, cost and footprint. His group has also been active in exploring new server architectures that combine “near threshold” technology and 3D chip stacking to drastically reduce system power consumption. They recently complete the tape-out of a 128-core multiprocessor that integrated the cores, caches and DRAM into a single 3D stack. The fabrication run was funded by a DARPA grant.
Finally, my group is exploring ways to build low power compact interconnect fabrics. We recently completed a compact 128 x 128 crossbar architecture that can sustain a bi-section bandwidth of about 1.3 terabits / second while consuming less than 130 mW.

My research spans the following broad topics in the field of computer systems:

•Computer Architecture and Compilers – I am interested in a wide range of aspects involving the intersection of architecture and compilers. My specific focus is on performance, power consumption, and reliability issues for embedded and multi-core processors.
•Reconfigurable Computing – I look into uses of reconfigurable computing as a general enabling technology. Specifically, I focus on the acceleration of various diverse application domains such as cryptography, image and video processing, and data mining, as well as the use of multi-FPGA platforms for fast system prototyping.
•Security – I study the use of automation to address various aspects of security and trust. Past projects in this area include the design and analysis of compiler and architectural approaches to improve software security, as well as an investigation into design methodologies that reduce the effectiveness of side-channel attacks on hardware/software systems.

Parallel computing

My research explores hardware and software tradeoffs to improve system performance, system reliability, and system security. The use of digital integrated circuits (ICs) for mission-critical, safety, defense, and communication applications has highlighted the need for enhanced reliability and improved security. As fabrication technology advances, digital ICs will become more vulnerable to soft errors from strikes by ionized particles. However, mitigation strategies that focus only upon devices or logic gates will consume excessive amounts of area and power, and could limit performance. At the same time, there is a constant threat of hardware and software tampering through malicious activity. Inherent architectural vulnerabilities must be removed to reduce the probability of a successful attack. My current work includes: (1) hardware synthesis techniques to mitigate soft errors in the microarchitecture and (2) detection of hardware trojans in fabricated circuits.

My primary research interest is in computer architecture. As systems continue to incorporate more transistors and cores on chip, parallelism and reliability are two big roadblocks of the computer evolution. With these emerging challenges, my research effort focuses on efficient architectural support for many-core computing and extremely low-cost error resilient architectures.

- Scalable, QoS-aware, Energy-Efficient Multi-core Memory Systems
- Scalable, QoS-aware, and Energy-Efficient Interconnection Networks
- Asymmetric Multi-core Systems
- Enabling and Exploiting Emerging Memory Technologies
- Architectural Support for Safe Languages
- Architectural Support for Virtualization and Multi-Core Operating Systems
- Resource Management

Other projects are also possible. Feel free to contact me for more information.

Interpretation of human activities using wireless sensor networks and their applications to elder monitoring, security and sensing.

Cyber-Physical Systems for energy management in next-generation intelligent buildings.

Sensor network architectures for the above mentioned systems.

I am a researcher at Intel Labs Pittsburgh (in the CIC building on CMU campus). I am looking for a Post Doc to work on exploiting new memory technologies for database systems in the Hi-Spade project (http://www.pittsburgh.intel-research.net/projects/hi-spade/). Flash-based Solid State Drives (SSDs) are becoming more and more popular in mainstream computing today. Phase change memory is a promising non-volatile memory technology to replace DRAM main memory in 5-10 years. These new memory technologies are dramatically changing the traditional memory hierarchy. It is important to understand the impact of and exploit the new hierarchy for data-intensive applications. In the Hi-Spade project, we are particularly interested in exploiting the new memory technologies for important database operations in OLTP and data warehousing. I published papers mainly in database systems and computer architecture, including award-winning papers in ICDE, SIGMOD, and ISCA. I have served on program committees of all major database conferences (SIGMOD, VLDB, ICDE).

Programming models, languages and compilers for efficient parallel execution.

High-performance and energy-efficient cache designs for large-scale multicore architectures; architecture and runtime support for emerging memory technologies; architecture and runtime support for novel parallel programming models (deterministic parallelism, disciplined parallelism); architectural and runtime support, and programming models for variable-fidelity computing; cross-layer reliable systems, where the reliability goal is achieved through the cooperation of all the abstraction layers, from circuits to architecture to the operating system; programming models, runtime environments and memory hierarchy designs for heterogeneous multicores; programming models, and runtime and architecture support for energy-aware computing; impact of memristors on architecture, memory hierarchy and systems software; novel database management systems for emerging multicore architectures and memory technologies

1. Designing efficient algorithms for networking, security, and database applications. My current focus is on efficient packet processing algorithms used on core Internet devices such as routers and IDS/IPSes.

2. Designing efficient privacy preserving protocols for practical problems. My current focus is on privacy and integrity preserving queries.

More information is on my homepage http://www.cse.msu.edu/~alexliu/

I am interested in microarchitecture, architecture, and applications and focus on building end-to-end systems driven by technology constraints in the next 10 years. I believe energy efficiency and reliability are the two important issues for this decade and beyond. I am looking at fundamentally new ways of exposing hardware reliablity to software and extracting unprecedented levels of hardware energy efficiency through specialization. I take a full-system view in my research and look at transformative and risky ways to address these fundamental problems.

Postdoc positions available for Customizable Domain-Specific Computing (CDSC) supported under the National Science Foundation Expeditions in Computing Award. Research topics include novel customizable architecture, domain-specific modeling, compilation, and runtime systems. Domain-specific applications.

Heterogeneous many-core system, architecture

High Performance Reconfigurable Computing

Hardware acceleration technologies (e.g., FPGA, GPGPU), programming model and applications

Hardware design (e.g., image processing, cryptography)

Cache policy design in Solid-State Drives and emerging data storage devices

Anura Jayasumana is a Professor of electrical and computer engineering at Colorado State University, where he also holds a joint appointment as Professor of computer science. He directs the Computer Networking Research Laboratory at CSU, and is a member of NSF Engineering Research Center for Collaborative Adaptive Sensing of the Atmosphere. At CSU, he has supervised over 15 Ph.D. and 45 M.S. theses, and taught courses ranging from freshmen undergraduate courses to specialized graduate courses in Electrical and Computer Engineering. He has published over 200 research papers and a book. He has served as a consultant to numerous companies ranging from start-ups to Fortune 100 companies.

My research group focuses on computer architecture, parallel processing, computer systems performance analysis, and high-performance storage systems. We have a particular emphasis on the interaction of software and compilers with computer architecture, and the interaction of computer architecture and circuits. Current projects include: novel architectures for new technologies, stochastic computing, heterogeneous parallel computing (e.g. conventional processors with GPUs and Cell processors), high-performance scientific computing, data de-duplication, incorporating flash memory into scalable systems. We work closely with researchers in geophysics, databases, compilers, and operating systems.

Current Research Interests: My current research principally revolves around the broad topic Network on Chip (NoC), which has emerged as the communication backbone for multi-core chips. With my graduate students and collaborators I am working on the following projects.
•On-chip wireless communication network: Recent research has established characteristics of silicon integrated antennas for intra- and inter-chip communication. Moreover excellent emission and absorption characteristics leading to antenna like behavior in carbon nanotubes (CNTs) are observed recently. In this project we are working on the design methods for wireless NoCs with different types of on-chip antennas.
•Reliable and Low Power NoC: We have designed a family of joint crosstalk avoidance and multiple error correction codes (CAC/MEC) and demonstrated how a low power and reliable NoC can be designed by incorporating these CAC/MEC codes.
•Three dimensional (3D) NoC: NoC has emerged as the communication backbone for the multi-core chips. The performance improvement arising from the architectural advantages of NoCs will be significantly enhanced if 3D ICs are adopted as the basic fabrication methodology. The amalgamation of two emerging paradigms, NoC and 3D IC, allows for the creation of new structures that enable significant performance enhancements over more traditional solutions. In this project we are investigating characteristics of 3D NoCs.
•Network-on-chip based hardware accelerators for Biocomputing: The gap between data generation and data processing is rapidly widening in biocomputing applications, and to close this gap it is imperative to assimilate the latest of breakthroughs in the Integrated Circuit (IC) design community into mainstream biocomputing research. Integrating huge number of processing cores on a single chip can help realize orders of magnitude improvement in performance and eventually will bridge the gap between data generation and data processing. In this project our aim is to design NoC-based hardware accelerators for different biocomputing applications, like sequence alignment and phylogenetic tree construction

Early 3D Chip Planning

Realizing the potential that 3D VLSI offers, requires system and chip architects to consider a broader range of options than the may have thought about in the past. For example, the placement of functions on the different strata of a 3D VLSI chip impacts a variety of features and attributes whose implications are not fully known: latencies that affect performance; power density that affects temperatures, power distribution demand and reliability; number and location of TSVs (thru-silicon vias) that affect wiring congestion and logic layout; proximity of macros that affects noise coupling among layers, etc.

To improve the linkage between the performance modeling environment and the physical planning environment for 3D VLSI chip design, we are integrating diverse forms of analysis to enable early and accurate identification of performance, power density, thermal, C4 and TSV current, IR drop and other physical issues. The goal is to help system architects to rapidly make trade-off decisions. In addition, we are developing a linkage from the early abstract design to an initial “detailed” layout that captures the design decisions and enable detailed chip integration. Such an integrated 3D planning environment provides an environment for new optimization tools to further assist system architectsarlky arl

My interests span most of “systems”, broadly construed, with a unifying theme of parallelism and concurrency. With the rise of multicore processors, this theme has become central to nearly every aspect of system design. Building on past work in synchronization and microarchitecture, the group here at Rochester has played a leading role in the development of transactional memory. We’re also working on concurrent programming models and language design (for both mainstream and scripting languages), heterogeneous and multicore architecture, and distributed systems with multicore nodes. As the author of a major programming languages text, I’m also deeply interested in how to integrate concurrency into the undergraduate curriculum.

Our group works on design and implementation aspects of security in embedded systems design. We work on secure embedded hardware and software required to implement secure prototocols and cryptography. Where needed, we develop appropriate countermeasures against physical attacks. Our team’s expertise covers multiple abstraction levels, including circuits, hardware micro-architecture, firmware, and platform-specific software. We also work on methodologies, with a focus on the trade-off between system performance, system cost, and system security.

Current research topics include: compilation using many-core CPUs (including GPUs), high-ILP microarchitectures, parallel libraries for biomedical imaging, hardware/software reliability, virtualization performance, architectural features for security, and intrusion detection and taint analysis.

The research thrust of the Nano-Computing Research Group, in the department of Electrical Engineering, lies predominantly in modeling, synthesizing, and harnessing the computing promises and logical aspects of innovative nano-devices. Technologies such as sub-45nm CMOS, and Magnetic Logic and memory devices, several flavors of Quantum Cellular Automata (QCA), to name a few, are systems that operate in a novel manner and could have substantial impact on the computing world. We at the NCRG see a significant need to investigate such devices, and therefore, endeavor into several key areas throughout the design automation process, such as model creation, low-high level architecture design, the fabrication of novel nano-devices, and the experimental characterization of those nano-devices. The theoretical foundation of our research framework is graph-based probabilistic models like Bayesian Networks, representing the dependencies in logic that characterizes the physical behavior of the device. We extensively use E-Beam lithography to fabricate our devices and analyze them using AFM, at our University’s Nano-Materials and Nano-Science Research Center (NNRC).

Our lab includes advaced research in the areas of computer graphics and a broad array of visual computing topics from input sensors to amatuer content creation (3D model extraction from photos etc), to procedural representations of avatars and animations of same, there are some elements of Video and Image processing using complex statistical algorithms and explorations of challenges / new application scenarios made possible by the evolution of Mobile Internet Devices and the sensors that are expected to be attached, also Mobile Augmented Reality whereby such MIDs can add value to the experience by leveraging the sensor inputs along with direct connection to the internet.

Interested in against-conventional-wisdom approaches to solve the most challenging problems in computer architecture. Currently am working on a novel execution model to program sequentially (i.e.,deterministic execution with no synchronization constructs), but run programs in parallel, on stock hardware. If you are interested in going against the tide of conventional wisdom in attacking one of the most challenging problems facing the computer industry, consider coming to Wisconsin.

My work at Google focuses on improving the programmability and performance of web applications delivered over the internet. Recent years have seen an explosion in size and scope of web applications to the extent that they are now straining the capabilities of today’s web execution frameworks. I am investigating the evolution of these frameworks to better handle greater client-side compute requirements, scalability, programmability, and security.

Norm’s research interests include implications of emerging nanophotonic technology on computer systems, low-latency high-bandwidth networking for cluster computing, heterogeneous chip multiprocessor architectures, and blade system architectures.

Fault Tolerance, Reliability, Computer Architecture, Power management, Performance and power analysis, Soft Errors, System Design, Low power circuits, system design methods

I am interested in innovative research which spans compiler/architecture boundary
particularly alternative forms of parallelism, including memory-level and instruction level parallelism. Current research projects include a new program representation which permits unrestricted code motion, compiler algorithms for optimizations on this representation as well as new micro-architecture designs capable of directly executing this representation. The representation has its roots in data-flow, demand driven and instruction-level parallelism. I am also interested in domain specif?c languages particularly automatic generation of micro-architecture simulators.

My research interests are in the area of asynchronous (i.e. clockless) and mixed-timed circuits and systems.

Specifically, I am interested in design and test of asynchronous systems, including: (i) high-level specification and translation; (ii) performance analysis; (iii) system-level optimization, including bottleneck detection and alleviation; (iv) mapping to asynchronous pipelined circuits; and (v) test and testability issues.

In addition to pure asynchronous systems, I am interested in mixed-timed systems as well, including globally-asynchronous locally-synchronous systems (GALS), latency-insensitive design, elastic systems (both synchronous and asynchronous), and on-chip-networks (NOCs).

My research group actively pursues work at various levels of abstraction: from circuit level (asynchronous pipeline circuits), to microarchitecture level, to system level. The work also targets several application areas in high-speed and low-power computing.

A particular area of research interest is mobile low-power graphics hardware. In collaboration with Prof. Anselmo Lastra, we are developing architectural techniques for ultra-low-power graphics, suitable for handheld gaming devices, cell phones, PDAs, etc. An active line of investigation is to dynamically trade off solution quality for energy savings when energy conservation is critical. This project also targets several levels of design abstraction: circuit, microarchitecture, system, memory, and software.

Finally, I am interested in exploring the application of asynchronous design techniques for the next-generation silicon and non-silicon emerging technologies, such as nano, quantum and biologically-inspired computing.

I am interested in VLSI design automation area generally, with specific focus in the areas of system level verification and simulation. I am also interested in static circuit timing, statistical static timing, circuit tuning and optimization.

The current research of the Scalable Computing Software (SCS) group is focused on reducing data access delay and enhancing fault-tolerant computing. Modern High-End Computing (HEC) systems become unprecedented fast in terms of CPU speed and unprecedented large in terms of system ensemble size. However, the technology advance is biased and unbalanced. The fast in CPU speed is worsen the memory-wall problem and the increasing in ensemble size makes fault-tolerant vital of HEC. We have proposed a new I/O architecture for HEC. Unlike traditional I/O, our architecture is based on a novel “Server-Push” model where a data access server, called File Access Server (FAS), proactively “pushes” data in time from a file server to the compute node’s memory. Here the “pushes” includes both “push up” (read) and “push down” (write). This concept is applicable to cache and memory data access as well. In fault tolerance, we combine the merits of both the newly emerged proactive fault tolerant approach and the traditional checkpointing approach to develop the FENCE (Fault awareness ENabled Computing Environment) environment. The SCS group currently has four NSF supported projects, two DoE supported projects, and one industry supported project in the about research areas. These research projects are in collaboration with the Argonne National Laboratory and the Fermi National Accelerator Laboratory, and are partially carried in the two national laboratories. Prof. Xian-He Sun is the director of the SCS laboratory, and a guest faculty of Argonne and Fermi laboratory. More information regarding the SCS laboratory can be found at www.cs.iit.edu/~scs/.

Power analysis

Research on VLSI Design Automation. More specifically tools targeting timing and signal integrity, power integrity, clock design and optimization, gate level modeling, circuit and interconnect analysis.
Numerical methods and scientific computing applied to above subjects.

I am currently coordinating research program to explore the opportunities of benefiting from a structured Network on chip organization in NEC chip architectures. My main research interests include the development of methodologies and tools for electronic system level design. I focus, in particular, on design and synthesis of reusable platforms, networks on chip and hardware/software integration challenges.

Programming Models and Productivity, Hardware Accelerators, and Manycore Processors.

PROJECT 1 is developing tooling and analysis techniques to enable
performance optimization in support of large commercial workloads in
the massive multicore era in which systems have hundreds or thousands
of processor cores. PROJECT 1 involves working with large-scale,
commercial applications with an eye towards dramatic improvements in
the performance of critical enterprise software deployments. This
project would benefit from postdocs whose research focuses on such
issues and who have experience with deployment and performance
analysis of multi-tier web applications, and more particularly
experience with Java programming, scripting (Javascript, Awk, Perl),
Java EE, database setup and tuning.

PROJECT 2 also focuses on future system architectures with large
numbers of multicore processors, but with a particular focus on how
such systems incorporate solid state disk / memory. PROJECT 2 is
analyzing how software can best take advantage of SSD and multicore
advances and what algorithms and architectures are best suited to
these systems — with approaches again focused on critical enterprise
workloads. This project would benefit from postdocs whose research
focuses on such issues and who have experience in storage systems and
disk modeling and with good knowledge of system benchmarking,
performance modelling, flash memory design, and interfaces such as
Sata and PCIe.

I am generally interested in parallel hardware architectures and programming models. I am also very interested in FPGA prototyping to validate architecture ideas, and make them real. Currently, I am involved in architecting a massively parallel machine learning processor, and its associated software stack.

Currently, my main focus is on realizing Claytronics, a form of
programmable matter. Programmable matter is an ensemble of computing
elements which can be programmed to work together to produce changes
in the physical properties of the ensemble. I am interested in
post-doctoral fellows who have broad interests. Particular projects
in the upcoming year: (1) realizing claytronics hardware (cm-scale
modular robots, mm-scale MEMS based robots, and bio-based units), (2)
Programming massively distributed systems (programmable matter, sensor
networks, etc.) using declarative approaches, (3) Ensemble based
applications (E.g., distributed planning, dynamic motion, etc.)

logic and physical synthesis, high performance circuit design and CAD, Circuit Design.

My research focuses on using 3D stacking to improve reliability in high performance processors. My research group also works on data center efficiency improvement issues primarily from the ICT infrastructure view point. I also work on energy efficient sensor management for body area networks for continuous and real time health monitoring.

Prior to my teaching career, I worked in industrial research labs for 6 years; first at the Intel Microprocessor Research Labs as a senior researcher for five years and then at the Nokia Research Center Palo Alto as a visiting research faculty for eight months. At Nokia my research focused on mobile platform services. At Intel my research focused on computer systems architecture spanning the entire computer system design space; from new silicon technologies at that hardware level to systems software analysis of server workloads.

My research lies broadly in the areas of electronic design automation and computer architecture. More specifically, my recent research projects concern energy efficient synchronization techniques for embedded architectures, post-silicon timing analysis and verification tool development, low-overhead techniques for on-line error detection, and noise analysis and design of future nanoscale systems.

My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels. As chips grow increasing larger and faster, power and design-time requirements become more aggressive, and timing variability becomes a critical factor, there are increasing challenges in assembling centrally-controlled synchronous systems. My goal is to make asynchronous digital design a viable option for designers.

Asynchronous design promises several key benefits: low power (where components are activated only when needed); high performance (some asynchronous systems can obtain average-case operating speeds, rather than be bound to worst-case); great robustness to timing variability and unpredictability; and modularity and composability.

There is a surge of interest in asynchronous design recently, for a variety of areas and challenges: (i) designing and integrating complex scalable digital systems and networks-on-chip (with multiple clock domains), which gracefully accommodate variability; (ii) ultra-low-energy and low-EMI applications (by dispensing with the global clock, and operating ‘on-demand’); (iii) embedded systems.

Recently, Philips has sold over 300 million asynchronous chips for moderate-performance
embedded systems: digital smartcards, passports, cell phones, pagers, and automotive. Through its incubated spinoff startup company, Handshake Solutions, an asynchronous ARM processor is offered through ARM Ltd. with 2.8x lower power than a comparable synchronous ARM (see http://www.handshakesolutions.com/products_services/ARM996HS/Index.html).

In my research group, there are currently six main project areas: (i) developing computer-aided design (CAD) tools and algorithms for the synthesis, optimization, analysis and verification of asynchronous designs, both for individual controllers and for entire systems; (ii) developing practical high-speed VLSl circuit structures, such as pipeline circuits; (iii) ultra-low-energy design (through computing-on-demand) of sensors and DSP’s; (iv) designing robust and flexible mixed-timing interface circuits, and asynchronous interconnect networks (NOCs), to accommodate mixed-clock and clocked/asynchronous timing domains, to enable the design of complex scalable multi-core systems with components operating at different clock rates; and (v) high-performance/low-energy arithmetic circuits; (vi) promoting technology transfer of my asynchronous CAD tools and circuit design styles to industry.

Recent successes from my group include:

- technology transfer to NASA Goddard Space Center:

Jointly designed experimental chip for laser space measurement, including use of our Minimalist CAD package (for controller design), exhibiting much lower area and power than comparable synchronous design

- technology transfer to IBM Yorktown:

Fabricated FIR filter chip (using async core with sync interfaces) exhibiting higher-throughput and lower-latency than the best comparable synchronous design from IBM

- tool development: CaSCADE package

CaSCADE is an asynchronous tool environment (jointly developed by Columbia/USC), with 3 Columbia tools, all downloadable with tutorials and user interfaces: (i) Minimalist (for asynchronous controllers); (ii) DES Analyzer (for performance analysis/timing verification of concurrent systems); and (iii) ATN-OPT (for robust asynchronous datapath design).

Static timing analysis and statistical timing analysis of VLSI circuits, process variation analysis, at speed structural testing of digital circuits, circuit analysis, signal integrity, optimization of digital circuits, coupling noise analysis in digital circuits.

High Performance Low Power Interconnect
Analysis, Design, and Optimization

We plan to continue, and further extend our work on interconnect
analysis, design, and optimization with an emphasis on high speed
and low power under parameter variations.
Our research tackles the challenges of the power ground distributions,
clock networks, and signal buses as the technology scales.

(1) power ground distribution: As the VLSI technologies scale,
the power noises integrity have created serious signal integrity
problems. The conventional methodology of bounding the target impedance
has become very expensive. Our goal is to suppress the peak voltage
noises instead of the peak impedance. We will identify the worst
stimulus of the system, devise robust controls of the system
activities, adjust the equivalent series resistance of the
decoupling capacitors to restraint the antiresonance, and
allocate the power pins of chip carriers and PC boards for
global optimization.

(2) clock distribution: The analysis of the clock timing has
become one bottleneck of the design process in terms of CPU
time and memory storage. Recently released location-based
on-chip variations (LOCV) standard was proposed to tackle the
statistical parameter variations. However, the LOCV standard
aggravates the demand of computation power and memory capacity.
We will study new algorithms to speed up the LOCV analysis of
common segments of clock paths and reduce the memory requirement.

(3) on-chip shared bus logic and topology:
For on-chip buses, the signal delay and power consumption
are becoming more significant as the technology scales.
We have invented a graph topology with gated logic to improve
the system performance. We will continue to study the design
algorithms and circuit architectures for the best performance
of the buses.

We have a number of research projects in networking, data storage and cyber physical systems. They are listed below.
1. Mass Storage Systems: We are investigating new storage models like object-oriented storage devices and new technology like Solid State d
Drives (SSD). We are especially interested in integrating SSD into the current storage hierarchy to solve a number of challenging issues for storage systems. We are also investigating the security/privacy of data and long-term data preservation issues.
2. Networking Research: We are interested in the future Internet with a large number of embedded processors and sensors connected through the Internet. How the Internet react to situation changes? How mobile and sensor devices will be fully integrated into future Internet?
3. Cyber Physical Systems: We are investigating how to make next generation air transport systems to be safers, more efficient and more secure. We are also interesting the vehicle to vehicle networks. We believe that in the near future not only all vehicles can communicate with each other, but also each vehicle will be able to connect to Internet. What are the technique challenges for building such an infrastructure are the focuses of our study.

Research and development of software, algorithms, tools, and methodologies in the area of Electronic Design Automation (EDA) for Integrated Circuit (IC) and System Designs.

My current research focuses on (1) multi-layer design, ranging from software down to device, for robust circuits and systems, and (2) solar energy and IT for smart grid

My department at Watson conducts research in several areas of design automation.
Circuit and Interconnect Analysis
Leadership in Statistical Timing, Circuit Analysis, Power Noise Analysis
Logic and Physical Synthesis
Synthesis-Placement-Routing integration, Sequential Synthesis, Boolean Optimization
Layout Analysis and Optimization
DFM, custom design automation
System Level Design
Early Architectural Exploration, Static code analysis

Multiprocessor architectures, parallel and distributed processing, I/O architectures, application oriented networking, routers

High-Performance Computing, Data Intenstive Computing, Parallel I/O and storage, data mining, computer architecture, security, business, medical and bioinformatics applications, power aware systems

Broadly speaking, my research areas fall in Computer Engineering which is at the intersection of Computer Science and Electrical Engineering. In this domain, my research focuses on nearly all aspects of digital VLSI circuits and systems design, leading to design automation and computer-aided design. These two areas ultimately require modeling, simulation, and mostly importantly, developing algorithms for optimization.

Topics within the circuits area include: performance analysis and optimization of nanoscale digital VLSI circuits, power optimization and low power design, logic synthesis and verification, digital system testing and design of novel digital circuit architectures such as threshold logic. Performance analysis and optimization also deals with statistical modeling of delay and power to account for process variations. A large part of my work is aimed at analytical work and algorithms with certain provable properties (as opposed to heuristics). In addition, I am also strongly interested in VLSI chip design leading to fabrication, and actual testing.

At the system level, my current research is focusing on energy management of portable, battery operated systems, system level dynamic power and thermal management of multi-core processors and design of multi-core processors.

I direct the VLSI Electronic Design Automation (VEDA) lab in the Computer Science and Engineering Dept at the Arizona State University. Students in this lab conducts research that addresses real-world challenges faced by chipmakers including manufacturing process variations and power/thermal constraints. They also work on technologies that show promise in the future like fuel-cell battery hybrids, and techniques for threshold logic synthesis. Our research covers multiple disciplines including electrical engineering, computer science and engineering, heat transfer, genetics, and optimization techniques.

Please visit http://veda.eas.asu.edu for further details and research publications.

Finally, my greatest source of joy is to work with graduate students and to joinlty create outstanding science. I am also deeply interested in entrepreneurial research and strongly encourage my students to build systems in addition to doing sound theoretical work.

Now a bit about me:

I am Consortium for Embedded Systems Chair Professor in the department of Computer Science and Engineering at the Arizona State University, Tempe AZ. I received the B.Math (Honors) from the University of Waterloo, Ontario, Canada, in 1976 and his M.S. and Ph.D degrees in electrical engineering from the University of Southern California in 1980 and 1985, respectively. During 1985-1992 I was on the faculty of the EE-Systems department of the University of Southern California. From 1992 to 2005 I was a professor in the Electrical and Computer Engineering department at the University of Arizona, in Tucson, AZ., and the Director of the NSF UA/ASU Center for Low Power Electronics. I became the director for the Consortium for Embedded Systems at ASU in 2006.

I have multiple projects in computer architecture and mobile systems with 8-10 PhD students funded. You would help supervise these students and be involved in all publication activity. We are currently developing applications and programming infrastructure for mobile phones using the Android platform. This research is being done in conjunction with the College of Medicine to develop support applications for elderly and disabled people. Computer architecture research involves low power processor architecture and next generation performance monitoring for multi-core platforms.

John Carter leads the Power Aware Systems research group at the IBM Austin Research Lab. At ARL, Dr. Carter and his teamare developing an array of technologies designed to dramatically reduce data center and server energy consumption as part of IBM’s Smart Planet initiative. These projects include: (i) integrating IT and facilities energy management (e.g., co-managing both computing resources and the electrical/cooling infrastructure), (ii) devising virtualization mechanisms that make energy-aware consolidation and task placement decisions, (iii) developing low-power high-performance storage servers that exploit flash and energy-aware caching/replication policies to reduce storage power, (iv) developing platform energy management solutions that actively manage the power consumed by individual components within a server (e.g., processors, memory, fans, and power supplies), (v) developing power management features for future IBM processors, and (vi) designing energy efficient high-performance (peta- and exa-scale) systems.

Prior to joining IBM, Dr. Carter was the Associate Director of the School of Computing at the University of Utah, where he led a number of research projects in the areas of multiprocessor computer architecture, distributed systems, and memory system design.

power-efficient chip microarchitectures, reliable processors and systems, technology-aware design and tools, pre-silicon integrated modeling and validation methodologies.

Our research focuses on software systems, broadly defined. Areas of interest range from building operating system mechanisms such as lightweight virtualized containers, multiprocessor deterministic record-replay tools, and process schedulers, to creating distributed system architectures for mobile, cloud and autonomic computing. For more information and recent papers, please visit the Network Computing Laboratory website: http://ncl.cs.columbia.edu.

The Superior Multiprocessor ARchitTecture (or SMART) Interconnects Group at USC investigates new architectures, techniques, and formalisms for achieving high-performance, energy-efficient, and reliable communication in parallel computer systems–from on-chip networks in multicore processors to interconnection networks in multiprocessor systems.

The postdoc who joins this group will have the opportunity to pursue specific research interests related to the above as well as to expand into other emerging areas such as interconnects for 3D stacked architectures, novel non-uniform cache architectures, and heterogeneous architectures. In addition to growing as a researcher under my guidance, the postdoc will have the opportunity to provide leadership in the group, serving as a mentor to graduate students and helping to provide guidance in their research activities.

I am interested in mechanisms that improve communication and reduce overheads for parallel systems. Currently, the emphasis is on multicore chips, and systems built from those chips, with emphasis on memory systems (e.g., coherence, transactional memory, prefetching), interconnection networks, and synchronization mechanisms.

My research interests include low-level compiler optimizations, tools for
supporting the development and maintenance of compilers, program
performance evaluation tools, predicting execution time, computer architecture
and embedded systems. Much of my recent research has involved compiler and
architectural support for low-power embedded processors. More information
about my background and research can be found on my home page,

http://www.cs.fsu.edu/~whalley.

My main research focus is on developing compiler algorithms, runtime systems, and tools that enable programmers to use a high-level programming style and modern languages, and yet still achieve high performance on modern architectures. I am particularly interested in effectively using processor memory hierarchies, and in memory management.

I am very interested in future architectures and their compilers that are a better match to current and future technology limits and constraints. Explicit Dataflow Graph Execution (EDGE) is the approach we are pursuing.

See my publications page for a sample of our recent results:

http://www.cs.utexas.edu/users/mckinley/papers.html